Referring to FIG. 1, a typical pad-level (input/output) block diagram of an integrated circuit 100 is shown. The integrated circuit 100 includes system input pins 102, system output pins 104, a system core logic 106, an IEEE Standard Test Access Port (TAP) controller 108, and boundary-scan (B/S) cells 110. Multiple pad circuits 112 are disposed between the B/S cells 110 and the output pins 104. Each pad circuit 112 has an input 114 for a data signal (i.e., DATA), an input 116 for an enable signal (i.e., EN), and another input 118 for one or more control signals (i.e., CNT).
The signals CNT control the configurable behavior of the output pad 112. Examples of the configurable behavior include drive strength, slew rate, and mode selections. The signals CNT are not required on simple pad circuits 112. The signals CNT are driven only by the system core logic 106. Here, a boundary scan test of the pad circuits 112 requires use of the system core logic 106 to set or default the signals CNT into a desired state. In many circumstances, configuring the system control logic 106 to present the signals CNT in the desired state requires a complicated sequence of events at the system input pins 102 and/or associated B/S cells 110.